262 lines
8.1 KiB
C
262 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
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*/
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#ifndef _CLK_SOPHGO_CV1800_IP_H_
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#define _CLK_SOPHGO_CV1800_IP_H_
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#include "clk-cv18xx-common.h"
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struct cv1800_clk_gate {
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struct cv1800_clk_common common;
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struct cv1800_clk_regbit gate;
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};
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struct cv1800_clk_div_data {
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u32 reg;
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u32 mask;
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u32 width;
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u32 init;
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u32 flags;
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};
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struct cv1800_clk_div {
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struct cv1800_clk_common common;
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struct cv1800_clk_regbit gate;
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struct cv1800_clk_regfield div;
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};
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struct cv1800_clk_bypass_div {
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struct cv1800_clk_div div;
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struct cv1800_clk_regbit bypass;
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};
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struct cv1800_clk_mux {
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struct cv1800_clk_common common;
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struct cv1800_clk_regbit gate;
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struct cv1800_clk_regfield div;
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struct cv1800_clk_regfield mux;
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};
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struct cv1800_clk_bypass_mux {
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struct cv1800_clk_mux mux;
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struct cv1800_clk_regbit bypass;
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};
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struct cv1800_clk_mmux {
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struct cv1800_clk_common common;
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struct cv1800_clk_regbit gate;
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struct cv1800_clk_regfield div[2];
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struct cv1800_clk_regfield mux[2];
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struct cv1800_clk_regbit bypass;
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struct cv1800_clk_regbit clk_sel;
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const s8 *parent2sel;
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const u8 *sel2parent[2];
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};
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struct cv1800_clk_audio {
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struct cv1800_clk_common common;
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struct cv1800_clk_regbit src_en;
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struct cv1800_clk_regbit output_en;
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struct cv1800_clk_regbit div_en;
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struct cv1800_clk_regbit div_up;
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struct cv1800_clk_regfield m;
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struct cv1800_clk_regfield n;
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u32 target_rate;
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};
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#define CV1800_GATE(_name, _parent, _gate_reg, _gate_shift, _flags) \
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struct cv1800_clk_gate _name = { \
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.common = CV1800_CLK_COMMON(#_name, _parent, \
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&cv1800_clk_gate_ops, \
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_flags), \
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.gate = CV1800_CLK_BIT(_gate_reg, _gate_shift), \
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}
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#define _CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \
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_div_reg, _div_shift, _div_width, _div_init, \
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_div_flag, _ops, _flags) \
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{ \
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.common = CV1800_CLK_COMMON(#_name, _parent, \
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_ops, _flags), \
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.gate = CV1800_CLK_BIT(_gate_reg, \
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_gate_shift), \
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.div = CV1800_CLK_REG(_div_reg, _div_shift, \
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_div_width, _div_init, \
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_div_flag), \
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}
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#define _CV1800_FIXED_DIV_FLAG \
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(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST)
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#define _CV1800_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift, \
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_fix_div, _ops, _flags) \
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{ \
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.common = CV1800_CLK_COMMON(#_name, _parent, \
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_ops, _flags), \
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.gate = CV1800_CLK_BIT(_gate_reg, \
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_gate_shift), \
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.div = CV1800_CLK_REG(0, 0, 0, \
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_fix_div, \
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_CV1800_FIXED_DIV_FLAG),\
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}
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#define CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \
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_div_reg, _div_shift, _div_width, _div_init, \
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_div_flag, _flags) \
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struct cv1800_clk_div _name = \
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_CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \
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_div_reg, _div_shift, _div_width, _div_init,\
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_div_flag, &cv1800_clk_div_ops, _flags)
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#define CV1800_BYPASS_DIV(_name, _parent, _gate_reg, _gate_shift, \
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_div_reg, _div_shift, _div_width, _div_init, \
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_div_flag, _bypass_reg, _bypass_shift, _flags)\
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struct cv1800_clk_bypass_div _name = { \
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.div = _CV1800_DIV(_name, _parent, \
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_gate_reg, _gate_shift, \
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_div_reg, _div_shift, \
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_div_width, _div_init, _div_flag, \
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&cv1800_clk_bypass_div_ops, \
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_flags), \
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.bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
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}
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#define CV1800_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift, \
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_fix_div, _flags) \
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struct cv1800_clk_div _name = \
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_CV1800_FIXED_DIV(_name, _parent, \
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_gate_reg, _gate_shift, \
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_fix_div, \
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&cv1800_clk_div_ops, _flags) \
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#define CV1800_BYPASS_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift, \
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_fix_div, _bypass_reg, _bypass_shift, \
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_flags) \
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struct cv1800_clk_bypass_div _name = { \
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.div = _CV1800_FIXED_DIV(_name, _parent, \
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_gate_reg, _gate_shift, \
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_fix_div, \
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&cv1800_clk_bypass_div_ops, \
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_flags), \
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.bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
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}
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#define _CV1800_MUX(_name, _parent, _gate_reg, _gate_shift, \
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_div_reg, _div_shift, _div_width, _div_init, \
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_div_flag, \
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_mux_reg, _mux_shift, _mux_width, \
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_ops, _flags) \
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{ \
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.common = CV1800_CLK_COMMON(#_name, _parent, \
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_ops, _flags), \
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.gate = CV1800_CLK_BIT(_gate_reg, \
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_gate_shift), \
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.div = CV1800_CLK_REG(_div_reg, _div_shift, \
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_div_width, _div_init, \
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_div_flag), \
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.mux = CV1800_CLK_REG(_mux_reg, _mux_shift, \
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_mux_width, 0, 0), \
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}
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#define CV1800_MUX(_name, _parent, _gate_reg, _gate_shift, \
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_div_reg, _div_shift, _div_width, _div_init, \
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_div_flag, \
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_mux_reg, _mux_shift, _mux_width, _flags) \
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struct cv1800_clk_mux _name = \
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_CV1800_MUX(_name, _parent, _gate_reg, _gate_shift, \
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_div_reg, _div_shift, _div_width, _div_init,\
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_div_flag, _mux_reg, _mux_shift, _mux_width,\
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&cv1800_clk_mux_ops, _flags)
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#define CV1800_BYPASS_MUX(_name, _parent, _gate_reg, _gate_shift, \
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_div_reg, _div_shift, _div_width, _div_init, \
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_div_flag, \
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_mux_reg, _mux_shift, _mux_width, \
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_bypass_reg, _bypass_shift, _flags) \
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struct cv1800_clk_bypass_mux _name = { \
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.mux = _CV1800_MUX(_name, _parent, \
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_gate_reg, _gate_shift, \
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_div_reg, _div_shift, _div_width, \
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_div_init, _div_flag, \
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_mux_reg, _mux_shift, _mux_width, \
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&cv1800_clk_bypass_mux_ops, \
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_flags), \
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.bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
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}
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#define CV1800_MMUX(_name, _parent, _gate_reg, _gate_shift, \
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_div0_reg, _div0_shift, _div0_width, _div0_init, \
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_div0_flag, \
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_div1_reg, _div1_shift, _div1_width, _div1_init, \
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_div1_flag, \
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_mux0_reg, _mux0_shift, _mux0_width, \
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_mux1_reg, _mux1_shift, _mux1_width, \
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_bypass_reg, _bypass_shift, \
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_clk_sel_reg, _clk_sel_shift, \
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_parent2sel, _sel2parent0, _sel2parent1, _flags) \
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struct cv1800_clk_mmux _name = { \
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.common = CV1800_CLK_COMMON(#_name, _parent, \
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&cv1800_clk_mmux_ops,\
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_flags), \
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.gate = CV1800_CLK_BIT(_gate_reg, _gate_shift),\
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.div = { \
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CV1800_CLK_REG(_div0_reg, _div0_shift, \
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_div0_width, _div0_init, \
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_div0_flag), \
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CV1800_CLK_REG(_div1_reg, _div1_shift, \
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_div1_width, _div1_init, \
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_div1_flag), \
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}, \
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.mux = { \
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CV1800_CLK_REG(_mux0_reg, _mux0_shift, \
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_mux0_width, 0, 0), \
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CV1800_CLK_REG(_mux1_reg, _mux1_shift, \
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_mux1_width, 0, 0), \
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}, \
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.bypass = CV1800_CLK_BIT(_bypass_reg, \
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_bypass_shift), \
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.clk_sel = CV1800_CLK_BIT(_clk_sel_reg, \
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_clk_sel_shift), \
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.parent2sel = _parent2sel, \
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.sel2parent = { _sel2parent0, _sel2parent1 }, \
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}
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#define CV1800_ACLK(_name, _parent, \
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_src_en_reg, _src_en_reg_shift, \
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_output_en_reg, _output_en_shift, \
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_div_en_reg, _div_en_reg_shift, \
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_div_up_reg, _div_up_reg_shift, \
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_m_reg, _m_shift, _m_width, _m_flag, \
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_n_reg, _n_shift, _n_width, _n_flag, \
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_target_rate, _flags) \
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struct cv1800_clk_audio _name = { \
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.common = CV1800_CLK_COMMON(#_name, _parent, \
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&cv1800_clk_audio_ops,\
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_flags), \
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.src_en = CV1800_CLK_BIT(_src_en_reg, \
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_src_en_reg_shift), \
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.output_en = CV1800_CLK_BIT(_output_en_reg, \
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_output_en_shift), \
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.div_en = CV1800_CLK_BIT(_div_en_reg, \
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_div_en_reg_shift), \
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.div_up = CV1800_CLK_BIT(_div_up_reg, \
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_div_up_reg_shift), \
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.m = CV1800_CLK_REG(_m_reg, _m_shift, \
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_m_width, 0, _m_flag), \
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.n = CV1800_CLK_REG(_n_reg, _n_shift, \
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_n_width, 0, _n_flag), \
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.target_rate = _target_rate, \
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}
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extern const struct clk_ops cv1800_clk_gate_ops;
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extern const struct clk_ops cv1800_clk_div_ops;
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extern const struct clk_ops cv1800_clk_bypass_div_ops;
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extern const struct clk_ops cv1800_clk_mux_ops;
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extern const struct clk_ops cv1800_clk_bypass_mux_ops;
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extern const struct clk_ops cv1800_clk_mmux_ops;
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extern const struct clk_ops cv1800_clk_audio_ops;
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#endif // _CLK_SOPHGO_CV1800_IP_H_
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