124 lines
3.9 KiB
C
124 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
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*/
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#ifndef _CLK_SOPHGO_CV1800_H_
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#define _CLK_SOPHGO_CV1800_H_
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#include <dt-bindings/clock/sophgo,cv1800.h>
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#define CV1800_CLK_MAX (CLK_XTAL_AP + 1)
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#define CV1810_CLK_MAX (CLK_DISP_SRC_VIP + 1)
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#define REG_PLL_G2_CTRL 0x800
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#define REG_PLL_G2_STATUS 0x804
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#define REG_MIPIMPLL_CSR 0x808
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#define REG_A0PLL_CSR 0x80C
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#define REG_DISPPLL_CSR 0x810
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#define REG_CAM0PLL_CSR 0x814
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#define REG_CAM1PLL_CSR 0x818
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#define REG_PLL_G2_SSC_SYN_CTRL 0x840
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#define REG_A0PLL_SSC_SYN_CTRL 0x850
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#define REG_A0PLL_SSC_SYN_SET 0x854
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#define REG_A0PLL_SSC_SYN_SPAN 0x858
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#define REG_A0PLL_SSC_SYN_STEP 0x85C
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#define REG_DISPPLL_SSC_SYN_CTRL 0x860
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#define REG_DISPPLL_SSC_SYN_SET 0x864
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#define REG_DISPPLL_SSC_SYN_SPAN 0x868
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#define REG_DISPPLL_SSC_SYN_STEP 0x86C
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#define REG_CAM0PLL_SSC_SYN_CTRL 0x870
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#define REG_CAM0PLL_SSC_SYN_SET 0x874
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#define REG_CAM0PLL_SSC_SYN_SPAN 0x878
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#define REG_CAM0PLL_SSC_SYN_STEP 0x87C
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#define REG_CAM1PLL_SSC_SYN_CTRL 0x880
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#define REG_CAM1PLL_SSC_SYN_SET 0x884
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#define REG_CAM1PLL_SSC_SYN_SPAN 0x888
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#define REG_CAM1PLL_SSC_SYN_STEP 0x88C
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#define REG_APLL_FRAC_DIV_CTRL 0x890
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#define REG_APLL_FRAC_DIV_M 0x894
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#define REG_APLL_FRAC_DIV_N 0x898
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#define REG_MIPIMPLL_CLK_CSR 0x8A0
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#define REG_A0PLL_CLK_CSR 0x8A4
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#define REG_DISPPLL_CLK_CSR 0x8A8
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#define REG_CAM0PLL_CLK_CSR 0x8AC
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#define REG_CAM1PLL_CLK_CSR 0x8B0
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#define REG_CLK_CAM0_SRC_DIV 0x8C0
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#define REG_CLK_CAM1_SRC_DIV 0x8C4
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/* top_pll_g6 */
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#define REG_PLL_G6_CTRL 0x900
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#define REG_PLL_G6_STATUS 0x904
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#define REG_MPLL_CSR 0x908
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#define REG_TPLL_CSR 0x90C
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#define REG_FPLL_CSR 0x910
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#define REG_PLL_G6_SSC_SYN_CTRL 0x940
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#define REG_DPLL_SSC_SYN_CTRL 0x950
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#define REG_DPLL_SSC_SYN_SET 0x954
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#define REG_DPLL_SSC_SYN_SPAN 0x958
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#define REG_DPLL_SSC_SYN_STEP 0x95C
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#define REG_MPLL_SSC_SYN_CTRL 0x960
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#define REG_MPLL_SSC_SYN_SET 0x964
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#define REG_MPLL_SSC_SYN_SPAN 0x968
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#define REG_MPLL_SSC_SYN_STEP 0x96C
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#define REG_TPLL_SSC_SYN_CTRL 0x970
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#define REG_TPLL_SSC_SYN_SET 0x974
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#define REG_TPLL_SSC_SYN_SPAN 0x978
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#define REG_TPLL_SSC_SYN_STEP 0x97C
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/* clkgen */
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#define REG_CLK_EN_0 0x000
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#define REG_CLK_EN_1 0x004
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#define REG_CLK_EN_2 0x008
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#define REG_CLK_EN_3 0x00C
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#define REG_CLK_EN_4 0x010
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#define REG_CLK_SEL_0 0x020
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#define REG_CLK_BYP_0 0x030
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#define REG_CLK_BYP_1 0x034
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#define REG_DIV_CLK_A53_0 0x040
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#define REG_DIV_CLK_A53_1 0x044
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#define REG_DIV_CLK_CPU_AXI0 0x048
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#define REG_DIV_CLK_CPU_GIC 0x050
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#define REG_DIV_CLK_TPU 0x054
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#define REG_DIV_CLK_EMMC 0x064
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#define REG_DIV_CLK_EMMC_100K 0x06C
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#define REG_DIV_CLK_SD0 0x070
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#define REG_DIV_CLK_SD0_100K 0x078
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#define REG_DIV_CLK_SD1 0x07C
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#define REG_DIV_CLK_SD1_100K 0x084
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#define REG_DIV_CLK_SPI_NAND 0x088
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#define REG_DIV_CLK_ETH0_500M 0x08C
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#define REG_DIV_CLK_ETH1_500M 0x090
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#define REG_DIV_CLK_GPIO_DB 0x094
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#define REG_DIV_CLK_SDMA_AUD0 0x098
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#define REG_DIV_CLK_SDMA_AUD1 0x09C
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#define REG_DIV_CLK_SDMA_AUD2 0x0A0
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#define REG_DIV_CLK_SDMA_AUD3 0x0A4
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#define REG_DIV_CLK_CAM0_200 0x0A8
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#define REG_DIV_CLK_AXI4 0x0B8
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#define REG_DIV_CLK_AXI6 0x0BC
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#define REG_DIV_CLK_DSI_ESC 0x0C4
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#define REG_DIV_CLK_AXI_VIP 0x0C8
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#define REG_DIV_CLK_SRC_VIP_SYS_0 0x0D0
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#define REG_DIV_CLK_SRC_VIP_SYS_1 0x0D8
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#define REG_DIV_CLK_DISP_SRC_VIP 0x0E0
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#define REG_DIV_CLK_AXI_VIDEO_CODEC 0x0E4
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#define REG_DIV_CLK_VC_SRC0 0x0EC
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#define REG_DIV_CLK_1M 0x0FC
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#define REG_DIV_CLK_SPI 0x100
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#define REG_DIV_CLK_I2C 0x104
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#define REG_DIV_CLK_SRC_VIP_SYS_2 0x110
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#define REG_DIV_CLK_AUDSRC 0x118
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#define REG_DIV_CLK_PWM_SRC_0 0x120
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#define REG_DIV_CLK_AP_DEBUG 0x128
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#define REG_DIV_CLK_RTCSYS_SRC_0 0x12C
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#define REG_DIV_CLK_C906_0_0 0x130
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#define REG_DIV_CLK_C906_0_1 0x134
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#define REG_DIV_CLK_C906_1_0 0x138
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#define REG_DIV_CLK_C906_1_1 0x13C
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#define REG_DIV_CLK_SRC_VIP_SYS_3 0x140
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#define REG_DIV_CLK_SRC_VIP_SYS_4 0x144
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#endif /* _CLK_SOPHGO_CV1800_H_ */
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