136 lines
3.8 KiB
YAML
136 lines
3.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SM4450 TLMM block
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maintainers:
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- Tengfei Fan <quic_tengfan@quicinc.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SM4450 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sm4450-tlmm
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reg:
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maxItems: 1
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interrupts: true
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 68
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gpio-line-names:
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maxItems: 136
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sm4450-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sm4450-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sm4450-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-5])$"
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- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, atest_char, atest_usb0, audio_ref_clk, cam_mclk,
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cci_async_in0, cci_i2c, cci, cmu_rng, coex_uart1_rx,
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coex_uart1_tx, cri_trng, dbg_out_clk, ddr_bist,
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ddr_pxi0_test, ddr_pxi1_test, gcc_gp1_clk, gcc_gp2_clk,
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gcc_gp3_clk, host2wlan_sol, ibi_i3c_qup0, ibi_i3c_qup1,
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jitter_bist_ref, mdp_vsync0_out, mdp_vsync1_out,
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mdp_vsync2_out, mdp_vsync3_out, mdp_vsync, nav,
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pcie0_clk_req, phase_flag, pll_bist_sync, pll_clk_aux,
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prng_rosc, qdss_cti_trig0, qdss_cti_trig1, qdss_gpio,
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qlink0_enable, qlink0_request, qlink0_wmss_reset,
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qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
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qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2, qup1_se3,
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qup1_se4, sd_write_protect, tb_trig_sdc1, tb_trig_sdc2,
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tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
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tgu_ch3_trigout, tmess_prng, tsense_pwm1_out,
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tsense_pwm2_out, uim0, uim1, usb0_hs_ac, usb0_phy_ps,
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vfr_0_mira, vfr_0_mirb, vfr_1, vsense_trigger_mirnat,
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wlan1_adc_dtest0, wlan1_adc_dtest1 ]
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required:
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- pins
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sm4450-tlmm";
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reg = <0x0f100000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 137>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-state {
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rx-pins {
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pins = "gpio23";
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function = "qup1_se2";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio22";
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function = "qup1_se2";
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bias-disable;
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};
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};
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};
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...
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