392 lines
14 KiB
C
392 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* nau8325.h -- Nuvoton NAU8325 audio codec driver
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*
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* Copyright 2023 Nuvoton Technology Crop.
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* Author: Seven Lee <WTLI@nuvoton.com>
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* David Lin <CTLIN0@nuvoton.com>
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*/
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#ifndef __NAU8325_H__
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#define __NAU8325_H__
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#define NAU8325_R00_HARDWARE_RST 0x00
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#define NAU8325_R01_SOFTWARE_RST 0x01
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#define NAU8325_R02_DEVICE_ID 0x02
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#define NAU8325_R03_CLK_CTRL 0x03
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#define NAU8325_R04_ENA_CTRL 0x04
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#define NAU8325_R05_INTERRUPT_CTRL 0x05
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#define NAU8325_R06_INT_CLR_STATUS 0x06
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#define NAU8325_R09_IRQOUT 0x09
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#define NAU8325_R0A_IO_CTRL 0x0a
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#define NAU8325_R0B_PDM_CTRL 0x0b
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#define NAU8325_R0C_TDM_CTRL 0x0c
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#define NAU8325_R0D_I2S_PCM_CTRL1 0x0d
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#define NAU8325_R0E_I2S_PCM_CTRL2 0x0e
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#define NAU8325_R0F_L_TIME_SLOT 0x0f
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#define NAU8325_R10_R_TIME_SLOT 0x10
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#define NAU8325_R11_HPF_CTRL 0x11
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#define NAU8325_R12_MUTE_CTRL 0x12
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#define NAU8325_R13_DAC_VOLUME 0x13
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#define NAU8325_R1D_DEBUG_READ1 0x1d
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#define NAU8325_R1F_DEBUG_READ2 0x1f
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#define NAU8325_R22_DEBUG_READ3 0x22
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#define NAU8325_R29_DAC_CTRL1 0x29
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#define NAU8325_R2A_DAC_CTRL2 0x2a
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#define NAU8325_R2C_ALC_CTRL1 0x2c
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#define NAU8325_R2D_ALC_CTRL2 0x2d
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#define NAU8325_R2E_ALC_CTRL3 0x2e
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#define NAU8325_R2F_ALC_CTRL4 0x2f
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#define NAU8325_R40_CLK_DET_CTRL 0x40
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#define NAU8325_R49_TEST_STATUS 0x49
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#define NAU8325_R4A_ANALOG_READ 0x4a
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#define NAU8325_R50_MIXER_CTRL 0x50
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#define NAU8325_R55_MISC_CTRL 0x55
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#define NAU8325_R60_BIAS_ADJ 0x60
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#define NAU8325_R61_ANALOG_CONTROL_1 0x61
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#define NAU8325_R62_ANALOG_CONTROL_2 0x62
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#define NAU8325_R63_ANALOG_CONTROL_3 0x63
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#define NAU8325_R64_ANALOG_CONTROL_4 0x64
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#define NAU8325_R65_ANALOG_CONTROL_5 0x65
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#define NAU8325_R66_ANALOG_CONTROL_6 0x66
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#define NAU8325_R69_CLIP_CTRL 0x69
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#define NAU8325_R73_RDAC 0x73
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#define NAU8325_REG_MAX NAU8325_R73_RDAC
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/* 16-bit control register address, and 16-bits control register data */
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#define NAU8325_REG_ADDR_LEN 16
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#define NAU8325_REG_DATA_LEN 16
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/* CLK_CTRL (0x03) */
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#define NAU8325_CLK_DAC_SRC_SFT 12
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#define NAU8325_CLK_DAC_SRC_MASK (0x3 << NAU8325_CLK_DAC_SRC_SFT)
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#define NAU8325_CLK_MUL_SRC_SFT 6
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#define NAU8325_CLK_MUL_SRC_MASK (0x3 << NAU8325_CLK_MUL_SRC_SFT)
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#define NAU8325_MCLK_SEL_SFT 3
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#define NAU8325_MCLK_SEL_MASK (0x7 << NAU8325_MCLK_SEL_SFT)
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#define NAU8325_MCLK_SRC_MASK 0x7
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/* ENA_CTRL (0x04) */
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#define NAU8325_DAC_LEFT_CH_EN_SFT 3
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#define NAU8325_DAC_LEFT_CH_EN (0x1 << NAU8325_DAC_LEFT_CH_EN_SFT)
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#define NAU8325_DAC_RIGHT_CH_EN_SFT 2
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#define NAU8325_DAC_RIGHT_CH_EN (0x1 << NAU8325_DAC_RIGHT_CH_EN_SFT)
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/* INTERRUPT_CTRL (0x05) */
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#define NAU8325_ARP_DWN_INT_SFT 12
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#define NAU8325_ARP_DWN_INT_MASK (0x1 << NAU8325_ARP_DWN_INT_SFT)
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#define NAU8325_CLIP_INT_SFT 11
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#define NAU8325_CLIP_INT_MASK (0x1 << NAU8325_CLIP_INT_SFT)
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#define NAU8325_LVD_INT_SFT 10
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#define NAU8325_LVD_INT_MASK (0x1 << NAU8325_LVD_INT_SFT)
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#define NAU8325_PWR_INT_DIS_SFT 8
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#define NAU8325_PWR_INT_DIS (0x1 << NAU8325_PWR_INT_DIS_SFT)
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#define NAU8325_OCP_OTP_SHTDWN_INT_SFT 4
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#define NAU8325_OCP_OTP_SHTDWN_INT_MASK (0x1 << NAU8325_OCP_OTP_SHTDWN_INT_SFT)
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#define NAU8325_CLIP_INT_DIS_SFT 3
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#define NAU8325_CLIP_INT_DIS (0x1 << NAU8325_CLIP_INT_DIS_SFT)
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#define NAU8325_LVD_INT_DIS_SFT 2
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#define NAU8325_LVD_INT_DIS (0x1 << NAU8325_LVD_INT_DIS_SFT)
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#define NAU8325_PWR_INT_MASK 0x1
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/* INT_CLR_STATUS (0x06) */
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#define NAU8325_INT_STATUS_MASK 0x7f
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/* IRQOUT (0x9) */
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#define NAU8325_IRQOUT_SEL_SEF 12
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#define NAU8325_IRQOUT_SEL_MASK (0xf << NAU8325_IRQOUT_SEL_SEF)
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#define NAU8325_DEM_DITH_SFT 7
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#define NAU8325_DEM_DITH_EN (0x1 << NAU8325_DEM_DITH_SFT)
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#define NAU8325_GAINZI3_SFT 5
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#define NAU8325_GAINZI3_MASK (0x1 << NAU8325_GAINZI3_SFT)
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#define NAU8325_GAINZI2_MASK 0x1f
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/* IO_CTRL (0x0a) */
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#define NAU8325_IRQ_PL_SFT 15
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#define NAU8325_IRQ_PL_ACT_HIGH (0x1 << NAU8325_IRQ_PL_SFT)
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#define NAU8325_IRQ_PS_SFT 14
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#define NAU8325_IRQ_PS_UP (0x1 << NAU8325_IRQ_PS_SFT)
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#define NAU8325_IRQ_PE_SFT 13
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#define NAU8325_IRQ_PE_EN (0x1 << NAU8325_IRQ_PE_SFT)
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#define NAU8325_IRQ_DS_SFT 12
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#define NAU8325_IRQ_DS_HIGH (0x1 << NAU8325_IRQ_DS_SFT)
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#define NAU8325_IRQ_OUTPUT_SFT 11
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#define NAU8325_IRQ_OUTPUT_EN (0x1 << NAU8325_IRQ_OUTPUT_SFT)
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#define NAU8325_IRQ_PIN_DEBUG_SFT 10
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#define NAU8325_IRQ_PIN_DEBUG_EN (0x1 << NAU8325_IRQ_PIN_DEBUG_SFT)
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/* PDM_CTRL (0x0b) */
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#define NAU8325_PDM_LCH_EDGE_SFT 1
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#define NAU8325_PDM_LCH_EDGE__MASK (0x1 << NAU8325_PDM_LCH_EDGE_SFT)
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#define NAU8325_PDM_MODE_EN 0x1
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/* TDM_CTRL (0x0c) */
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#define NAU8325_TDM_SFT 15
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#define NAU8325_TDM_EN (0x1 << NAU8325_TDM_SFT)
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#define NAU8325_PCM_OFFSET_CTRL_SFT 14
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#define NAU8325_PCM_OFFSET_CTRL_EN (0x1 << NAU8325_PCM_OFFSET_CTRL_SFT)
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#define NAU8325_DAC_LEFT_SFT 6
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#define NAU8325_NAU8325_DAC_LEFT_MASK (0x7 << NAU8325_DAC_LEFT_SFT)
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#define NAU8325_DAC_RIGHT_SFT 3
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#define NAU8325_DAC_RIGHT_MASK (0x7 << NAU8325_DAC_RIGHT_SFT)
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/* I2S_PCM_CTRL1 (0x0d) */
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#define NAU8325_DACCM_CTL_SFT 14
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#define NAU8325_DACCM_CTL_MASK (0x3 << NAU8325_DACCM_CTL_SFT)
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#define NAU8325_CMB8_0_SFT 10
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#define NAU8325_CMB8_0_MASK (0x1 << NAU8325_CMB8_0_SFT)
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#define NAU8325_UA_OFFSET_SFT 9
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#define NAU8325_UA_OFFSET_MASK (0x1 << NAU8325_UA_OFFSET_SFT)
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#define NAU8325_I2S_BP_SFT 7
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#define NAU8325_I2S_BP_MASK (0x1 << NAU8325_I2S_BP_SFT)
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#define NAU8325_I2S_BP_INV (0x1 << NAU8325_I2S_BP_SFT)
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#define NAU8325_I2S_PCMB_SFT 6
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#define NAU8325_I2S_PCMB_EN (0x1 << NAU8325_I2S_PCMB_SFT)
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#define NAU8325_I2S_DACPSHS0_SFT 5
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#define NAU8325_I2S_DACPSHS0_MASK (0x1 << NAU8325_I2S_DACPSHS0_SFT)
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#define NAU8325_I2S_DL_SFT 2
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#define NAU8325_I2S_DL_MASK (0x3 << NAU8325_I2S_DL_SFT)
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#define NAU8325_I2S_DL_32 (0x3 << NAU8325_I2S_DL_SFT)
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#define NAU8325_I2S_DL_24 (0x2 << NAU8325_I2S_DL_SFT)
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#define NAU8325_I2S_DL_20 (0x1 << NAU8325_I2S_DL_SFT)
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#define NAU8325_I2S_DL_16 (0x0 << NAU8325_I2S_DL_SFT)
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#define NAU8325_I2S_DF_MASK 0x3
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#define NAU8325_I2S_DF_RIGTH 0x0
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#define NAU8325_I2S_DF_LEFT 0x1
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#define NAU8325_I2S_DF_I2S 0x2
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#define NAU8325_I2S_DF_PCM_AB 0x3
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/* I2S_PCM_CTRL2 (0x0e) */
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#define NAU8325_PCM_TS_SFT 10
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#define NAU8325_PCM_TS_EN (0x1 << NAU8325_PCM_TS_SFT)
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#define NAU8325_PCM8BIT0_SFT 8
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#define NAU8325_PCM8BIT0_MASK (0x1 << NAU8325_PCM8BIT0_SFT)
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/* L_TIME_SLOT (0x0f)*/
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#define NAU8325_SHORT_FS_DET_SFT 13
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#define NAU8325_SHORT_FS_DET_DIS (0x1 << NAU8325_SHORT_FS_DET_SFT)
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#define NAU8325_TSLOT_L0_MASK 0x3ff
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/* R_TIME_SLOT (0x10)*/
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#define NAU8325_TSLOT_R0_MASK 0x3ff
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/* HPF_CTRL (0x11)*/
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#define NAU8325_DAC_HPF_SFT 15
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#define NAU8325_DAC_HPF_EN (0x1 << NAU8325_DAC_HPF_SFT)
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#define NAU8325_DAC_HPF_APP_SFT 14
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#define NAU8325_DAC_HPF_APP_MASK (0x1 << NAU8325_DAC_HPF_APP_SFT)
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#define NAU8325_DAC_HPF_FCUT_SFT 11
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#define NAU8325_DAC_HPF_FCUT_MASK (0x7 << NAU8325_DAC_HPF_FCUT_SFT)
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/* MUTE_CTRL (0x12)*/
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#define NAU8325_SOFT_MUTE_SFT 15
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#define NAU8325_SOFT_MUTE (0x1 << NAU8325_SOFT_MUTE_SFT)
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#define NAU8325_DAC_ZC_SFT 8
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#define NAU8325_DAC_ZC_EN (0x1 << NAU8325_DAC_ZC_SFT)
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#define NAU8325_UNMUTE_CTL_SFT 6
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#define NAU8325_UNMUTE_CTL_MASK (0x3 << NAU8325_UNMUTE_CTL_SFT)
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#define NAU8325_ANA_MUTE_SFT 4
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#define NAU8325_ANA_MUTE_MASK (0x3 << NAU8325_ANA_MUTE_SFT)
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#define NAU8325_AUTO_MUTE_SFT 3
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#define NAU8325_AUTO_MUTE_DIS (0x1 << NAU8325_AUTO_MUTE_SFT)
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/* DAC_VOLUME (0x13) */
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#define NAU8325_DAC_VOLUME_L_SFT 8
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#define NAU8325_DAC_VOLUME_L_EN (0xff << NAU8325_DAC_VOLUME_L_SFT)
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#define NAU8325_DAC_VOLUME_R_SFT 0
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#define NAU8325_DAC_VOLUME_R_EN (0xff << NAU8325_DAC_VOLUME_R_SFT)
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#define NAU8325_DAC_VOL_MAX 0xff
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/* DEBUG_READ1 (0x1d)*/
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#define NAU8325_OSR100_MASK (0x1 << 6)
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#define NAU8325_MIPS500_MASK (0x1 << 5)
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#define NAU8325_SHUTDWNDRVR_R_MASK (0x1 << 4)
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#define NAU8325_SHUTDWNDRVR_L_MASK (0x1 << 3)
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#define NAU8325_MUTEB_MASK (0x1 << 2)
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#define NAU8325_PDOSCB_MASK (0x1 << 1)
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#define NAU8325_POWERDOWN1B_D_MASK 0x1
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/* DEBUG_READ2 (0x1f)*/
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#define NAU8325_R_CHANNEL_Vol_SFT 8
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#define NAU8325_R_CHANNEL_Vol_MASK (0xff << NAU8325_R_CHANNEL_Vol_SFT)
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#define NAU8325_L_CHANNEL_Vol_MASK 0xff
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/* DEBUG_READ3(0x22)*/
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#define NAU8325_PGAL_GAIN_MASK (0x3f << 7)
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#define NAU8325_CLIP_MASK (0x1 << 6)
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#define NAU8325_SCAN_MODE_MASK (0x1 << 5)
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#define NAU8325_SDB_MASK (0x1 << 4)
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#define NAU8325_TALARM_MASK (0x1 << 3)
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#define NAU8325_SHORTR_MASK (0x1 << 2)
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#define NAU8325_SHORTL_MASK (0x1 << 1)
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#define NAU8325_TMDET_MASK 0x1
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/* DAC_CTRL1 (0x29) */
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#define NAU8325_DAC_OVERSAMPLE_SFT 0
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#define NAU8325_DAC_OVERSAMPLE_MASK 0x7
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#define NAU8325_DAC_OVERSAMPLE_256 1
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#define NAU8325_DAC_OVERSAMPLE_128 2
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#define NAU8325_DAC_OVERSAMPLE_64 0
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#define NAU8325_DAC_OVERSAMPLE_32 4
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/* ALC_CTRL1 (0x2c) */
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#define NAU8325_ALC_MAXGAIN_SFT 5
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#define NAU8325_ALC_MAXGAIN_MAX 0x7
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#define NAU8325_ALC_MAXGAIN_MASK (0x7 << NAU8325_ALC_MAXGAIN_SFT)
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#define NAU8325_ALC_MINGAIN_MAX 4
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#define NAU8325_ALC_MINGAIN_SFT 1
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#define NAU8325_ALC_MINGAIN_MASK (0x7 << NAU8325_ALC_MINGAIN_SFT)
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/* ALC_CTRL2 (0x2d) */
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#define NAU8325_ALC_DCY_SFT 12
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#define NAU8325_ALC_DCY_MAX 0xb
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#define NAU8325_ALC_DCY_MASK (0xf << NAU8325_ALC_DCY_SFT)
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#define NAU8325_ALC_ATK_SFT 8
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#define NAU8325_ALC_ATK_MAX 0xb
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#define NAU8325_ALC_ATK_MASK (0xf << NAU8325_ALC_ATK_SFT)
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#define NAU8325_ALC_HLD_SFT 4
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#define NAU8325_ALC_HLD_MAX 0xa
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#define NAU8325_ALC_HLD_MASK (0xf << NAU8325_ALC_HLD_SFT)
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#define NAU8325_ALC_LVL_SFT 0
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#define NAU8325_ALC_LVL_MAX 0xf
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#define NAU8325_ALC_LVL_MASK 0xf
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/* ALC_CTRL3 (0x2e) */
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#define NAU8325_ALC_EN_SFT 15
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#define NAU8325_ALC_EN (0x1 << NAU8325_ALC_EN_SFT)
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/* TEMP_COMP_CTRL (0x30) */
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#define NAU8325_TEMP_COMP_ACT2_MASK 0xff
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/* LPF_CTRL (0x33) */
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#define NAU8325_LPF_IN1_EN_SFT 15
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#define NAU8325_LPF_IN1_EN (0x1 << NAU8325_LPF_IN1_EN_SFT)
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#define NAU8325_LPF_IN1_TC_SFT 11
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#define NAU8325_LPF_IN1_TC_MASK (0xf << NAU8325_LPF_IN1_TC_SFT)
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#define NAU8325_LPF_IN2_EN_SFT 10
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#define NAU8325_LPF_IN2_EN (0x1 << NAU8325_LPF_IN2_EN_SFT)
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#define NAU8325_LPF_IN2_TC_SFT 6
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#define NAU8325_LPF_IN2_TC_MASK (0xf << NAU8325_LPF_IN2_TC_SFT)
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/* CLK_DET_CTRL (0x40) */
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#define NAU8325_APWRUP_SFT 15
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#define NAU8325_APWRUP_EN (0x1 << NAU8325_APWRUP_SFT)
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#define NAU8325_CLKPWRUP_SFT 14
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#define NAU8325_CLKPWRUP_DIS (0x1 << NAU8325_CLKPWRUP_SFT)
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#define NAU8325_PWRUP_DFT_SFT 13
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#define NAU8325_PWRUP_DFT (0x1 << NAU8325_PWRUP_DFT_SFT)
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#define NAU8325_REG_SRATE_SFT 10
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#define NAU8325_REG_SRATE_MASK (0x7 << NAU8325_REG_SRATE_SFT)
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#define NAU8325_REG_ALT_SRATE_SFT 9
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#define NAU8325_REG_ALT_SRATE_EN (0x1 << NAU8325_REG_ALT_SRATE_SFT)
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#define NAU8325_REG_DIV_MAX 0x1
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/* BIAS_ADJ (0x60) */
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#define NAU8325_BIAS_VMID_SEL_SFT 4
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#define NAU8325_BIAS_VMID_SEL_MASK (0x3 << NAU8325_BIAS_VMID_SEL_SFT)
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/* ANALOG_CONTROL_1 (0x61) */
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#define NAU8325_VMDFSTENB_SFT 14
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#define NAU8325_VMDFSTENB_MASK (0x3 << NAU8325_VMDFSTENB_SFT)
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#define NAU8325_CLASSDEN_SFT 12
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#define NAU8325_CLASSDEN_MASK (0x3 << NAU8325_CLASSDEN_SFT)
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#define NAU8325_DACCLKEN_R_SFT 10
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#define NAU8325_DACCLKEN_R_MASK (0x3 << NAU8325_DACCLKEN_R_SFT)
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#define NAU8325_DACEN_R_SFT 8
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#define NAU8325_DACEN_R_MASK (0x3 << NAU8325_DACEN_R_SFT)
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#define NAU8325_DACCLKEN_SFT 6
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#define NAU8325_DACCLKEN_MASK (0x3 << NAU8325_DACCLKEN_SFT)
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#define NAU8325_DACEN_SFT 4
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#define NAU8325_DACEN_MASK (0x3 << NAU8325_DACEN_SFT)
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#define NAU8325_BIASEN_SFT 2
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#define NAU8325_BIASEN_MASK (0x3 << NAU8325_BIASEN_SFT)
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#define NAU8325_VMIDEN_MASK 0x3
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/* ANALOG_CONTROL_2 (0x62) */
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#define NAU8325_PWMMOD_SFT 14
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#define NAU8325_PWMMOD_MASK (0x1 << NAU8325_PWMMOD_SFT)
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#define NAU8325_DACTEST_SFT 6
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#define NAU8325_DACTEST_MASK (0x3 << NAU8325_DACTEST_SFT)
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#define NAU8325_DACREFCAP_SFT 4
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#define NAU8325_DACREFCAP_MASK (0x3 << NAU8325_DACREFCAP_SFT)
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/* ANALOG_CONTROL_3 (0x63) */
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#define NAU8325_POWER_DOWN_L_SFT 12
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#define NAU8325_POWER_DOWN_L_MASK (0x3 << NAU8325_POWER_DOWN_L_SFT)
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#define NAU8325_POWER_DOWN_R_SFT 11
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#define NAU8325_POWER_DOWN_R_MASK (0x3 << NAU8325_DACREFCAP_SFT)
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#define NAU8325_CLASSD_FINE_SFT 5
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#define NAU8325_CLASSD_FINE_MASK (0x3 << NAU8325_CLASSD_FINE_SFT)
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#define NAU8325_CLASSD_COARSE_GAIN_MASK 0xf
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/* ANALOG_CONTROL_4 (0x64) */
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#define NAU8325_CLASSD_OCPN_SFT 12
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#define NAU8325_CLASSD_OCPN_MASK (0xf << NAU8325_CLASSD_OCPN_SFT)
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#define NAU8325_CLASSD_OCPP_SFT 8
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#define NAU8325_CLASSD_OCPP_MASK (0xf << NAU8325_CLASSD_OCPP_SFT)
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#define NAU8325_CLASSD_SLEWN_MASK 0xff
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/* ANALOG_CONTROL_5 (0x65) */
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#define NAU8325_MCLK_RANGE_SFT 2
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#define NAU8325_MCLK_RANGE_EN (0x1 << NAU8325_MCLK_RANGE_SFT)
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#define NAU8325_MCLK8XEN_SFT 1
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#define NAU8325_MCLK8XEN_EN (0x1 << NAU8325_MCLK8XEN_SFT)
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#define NAU8325_MCLK4XEN_EN 0x1
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/* ANALOG_CONTROL_6 (0x66) */
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#define NAU8325_VBATLOW_SFT 4
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#define NAU8325_VBATLOW_MASK (0x1 << NAU8325_VBATLOW_SFT)
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#define NAU8325_VDDSPK_LIM_SFT 3
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#define NAU8325_VDDSPK_LIM_EN (0x1 << NAU8325_VDDSPK_LIM_SFT)
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#define NAU8325_VDDSPK_LIM_MASK 0x7
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/* CLIP_CTRL (0x69)*/
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#define NAU8325_ANTI_CLIP_SFT 4
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#define NAU8325_ANTI_CLIP_EN (0x1 << NAU8325_ANTI_CLIP_SFT)
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/* RDAC (0x73) */
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#define NAU8325_CLK_DAC_DELAY_SFT 4
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#define NAU8325_CLK_DAC_DELAY_EN (0x7 << NAU8325_CLK_DAC_DELAY_SFT)
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#define NAU8325_DACVREFSEL_SFT 2
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#define NAU8325_DACVREFSEL_MASK (0x3 << NAU8325_DACVREFSEL_SFT)
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#define NAU8325_CODEC_DAI "nau8325-hifi"
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struct nau8325 {
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struct device *dev;
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struct regmap *regmap;
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int mclk;
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int fs;
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int vref_impedance_ohms;
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int dac_vref_microvolt;
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int clock_detection;
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int clock_det_data;
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int alc_enable;
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};
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struct nau8325_src_attr {
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int param;
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unsigned int val;
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};
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enum {
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NAU8325_MCLK_FS_RATIO_256,
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NAU8325_MCLK_FS_RATIO_400,
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NAU8325_MCLK_FS_RATIO_500,
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NAU8325_MCLK_FS_RATIO_NUM,
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};
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struct nau8325_srate_attr {
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int fs;
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int range;
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bool max;
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unsigned int mclk_src[NAU8325_MCLK_FS_RATIO_NUM];
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};
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struct nau8325_osr_attr {
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unsigned int osr;
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unsigned int clk_src;
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};
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#endif /* __NAU8325_H__ */
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