431 lines
11 KiB
C
431 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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*
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* Bluetooth support for Intel PCIe devices
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*
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* Copyright (C) 2024 Intel Corporation
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*/
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/* Control and Status Register(BTINTEL_PCIE_CSR) */
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#define BTINTEL_PCIE_CSR_BASE (0x000)
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#define BTINTEL_PCIE_CSR_FUNC_CTRL_REG (BTINTEL_PCIE_CSR_BASE + 0x024)
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#define BTINTEL_PCIE_CSR_HW_REV_REG (BTINTEL_PCIE_CSR_BASE + 0x028)
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#define BTINTEL_PCIE_CSR_RF_ID_REG (BTINTEL_PCIE_CSR_BASE + 0x09C)
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#define BTINTEL_PCIE_CSR_BOOT_STAGE_REG (BTINTEL_PCIE_CSR_BASE + 0x108)
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#define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG (BTINTEL_PCIE_CSR_BASE + 0x118)
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#define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG (BTINTEL_PCIE_CSR_BASE + 0x11C)
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#define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG (BTINTEL_PCIE_CSR_BASE + 0x12C)
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#define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR (BTINTEL_PCIE_CSR_BASE + 0x460)
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/* BTINTEL_PCIE_CSR Function Control Register */
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#define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA (BIT(0))
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#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT (BIT(6))
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#define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT (BIT(7))
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#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20))
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#define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET (BIT(31))
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/* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */
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#define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM (BIT(0))
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#define BTINTEL_PCIE_CSR_BOOT_STAGE_IML (BIT(1))
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#define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW (BIT(2))
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#define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN (BIT(10))
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#define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN (BIT(11))
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#define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON (BIT(16))
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#define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE (BIT(23))
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/* Registers for MSI-X */
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#define BTINTEL_PCIE_CSR_MSIX_BASE (0x2000)
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#define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0800)
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#define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0804)
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#define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0808)
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#define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x080C)
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#define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0810)
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#define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0814)
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#define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0880)
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#define BTINTEL_PCIE_CSR_MSIX_IVAR(cause) (BTINTEL_PCIE_CSR_MSIX_IVAR_BASE + (cause))
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/* Causes for the FH register interrupts */
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enum msix_fh_int_causes {
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BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0 = BIT(0), /* cause 0 */
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BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1 = BIT(1), /* cause 1 */
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};
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/* Causes for the HW register interrupts */
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enum msix_hw_int_causes {
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BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0 = BIT(0), /* cause 32 */
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};
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#define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
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/* Minimum and Maximum number of MSI-X Vector
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* Intel Bluetooth PCIe support only 1 vector
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*/
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#define BTINTEL_PCIE_MSIX_VEC_MAX 1
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#define BTINTEL_PCIE_MSIX_VEC_MIN 1
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/* Default poll time for MAC access during init */
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#define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US 200000
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/* Default interrupt timeout in msec */
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#define BTINTEL_DEFAULT_INTR_TIMEOUT 3000
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/* The number of descriptors in TX/RX queues */
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#define BTINTEL_DESCS_COUNT 16
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/* Number of Queue for TX and RX
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* It indicates the index of the IA(Index Array)
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*/
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enum {
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BTINTEL_PCIE_TXQ_NUM = 0,
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BTINTEL_PCIE_RXQ_NUM = 1,
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BTINTEL_PCIE_NUM_QUEUES = 2,
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};
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/* The size of DMA buffer for TX and RX in bytes */
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#define BTINTEL_PCIE_BUFFER_SIZE 4096
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/* DMA allocation alignment */
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#define BTINTEL_PCIE_DMA_POOL_ALIGNMENT 256
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#define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS 500
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/* Doorbell vector for TFD */
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#define BTINTEL_PCIE_TX_DB_VEC 0
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/* Number of pending RX requests for downlink */
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#define BTINTEL_PCIE_RX_MAX_QUEUE 6
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/* Doorbell vector for FRBD */
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#define BTINTEL_PCIE_RX_DB_VEC 513
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/* RBD buffer size mapping */
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#define BTINTEL_PCIE_RBD_SIZE_4K 0x04
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/*
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* Struct for Context Information (v2)
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*
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* All members are write-only for host and read-only for device.
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*
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* @version: Version of context information
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* @size: Size of context information
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* @config: Config with which host wants peripheral to execute
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* Subset of capability register published by device
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* @addr_tr_hia: Address of TR Head Index Array
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* @addr_tr_tia: Address of TR Tail Index Array
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* @addr_cr_hia: Address of CR Head Index Array
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* @addr_cr_tia: Address of CR Tail Index Array
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* @num_tr_ia: Number of entries in TR Index Arrays
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* @num_cr_ia: Number of entries in CR Index Arrays
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* @rbd_siz: RBD Size { 0x4=4K }
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* @addr_tfdq: Address of TFD Queue(tx)
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* @addr_urbdq0: Address of URBD Queue(tx)
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* @num_tfdq: Number of TFD in TFD Queue(tx)
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* @num_urbdq0: Number of URBD in URBD Queue(tx)
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* @tfdq_db_vec: Queue number of TFD
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* @urbdq0_db_vec: Queue number of URBD
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* @addr_frbdq: Address of FRBD Queue(rx)
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* @addr_urbdq1: Address of URBD Queue(rx)
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* @num_frbdq: Number of FRBD in FRBD Queue(rx)
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* @frbdq_db_vec: Queue number of FRBD
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* @num_urbdq1: Number of URBD in URBD Queue(rx)
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* @urbdq_db_vec: Queue number of URBDQ1
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* @tr_msi_vec: Transfer Ring MSI-X Vector
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* @cr_msi_vec: Completion Ring MSI-X Vector
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* @dbgc_addr: DBGC first fragment address
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* @dbgc_size: DBGC buffer size
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* @early_enable: Enarly debug enable
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* @dbg_output_mode: Debug output mode
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* Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) }
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* Bit[5] DBGC I/P { 0=BDBG, 1=DBGI }
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* Bits[6:7] DBGI O/P(relevant if bit[5] = 1)
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* 0=BT DBGC, 1=WiFi DBGC, 2=NPK }
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* @dbg_preset: Debug preset
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* @ext_addr: Address of context information extension
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* @ext_size: Size of context information part
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*
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* Total 38 DWords
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*/
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struct ctx_info {
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u16 version;
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u16 size;
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u32 config;
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u32 reserved_dw02;
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u32 reserved_dw03;
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u64 addr_tr_hia;
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u64 addr_tr_tia;
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u64 addr_cr_hia;
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u64 addr_cr_tia;
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u16 num_tr_ia;
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u16 num_cr_ia;
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u32 rbd_size:4,
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reserved_dw13:28;
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u64 addr_tfdq;
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u64 addr_urbdq0;
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u16 num_tfdq;
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u16 num_urbdq0;
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u16 tfdq_db_vec;
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u16 urbdq0_db_vec;
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u64 addr_frbdq;
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u64 addr_urbdq1;
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u16 num_frbdq;
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u16 frbdq_db_vec;
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u16 num_urbdq1;
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u16 urbdq_db_vec;
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u16 tr_msi_vec;
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u16 cr_msi_vec;
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u32 reserved_dw27;
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u64 dbgc_addr;
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u32 dbgc_size;
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u32 early_enable:1,
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reserved_dw31:3,
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dbg_output_mode:4,
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dbg_preset:8,
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reserved2_dw31:16;
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u64 ext_addr;
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u32 ext_size;
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u32 test_param;
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u32 reserved_dw36;
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u32 reserved_dw37;
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} __packed;
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/* Transfer Descriptor for TX
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* @type: Not in use. Set to 0x0
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* @size: Size of data in the buffer
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* @addr: DMA Address of buffer
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*/
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struct tfd {
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u8 type;
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u16 size;
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u8 reserved;
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u64 addr;
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u32 reserved1;
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} __packed;
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/* URB Descriptor for TX
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* @tfd_index: Index of TFD in TFDQ + 1
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* @num_txq: Queue index of TFD Queue
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* @cmpl_count: Completion count. Always 0x01
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* @immediate_cmpl: Immediate completion flag: Always 0x01
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*/
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struct urbd0 {
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u32 tfd_index:16,
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num_txq:8,
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cmpl_count:4,
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reserved:3,
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immediate_cmpl:1;
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} __packed;
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/* FRB Descriptor for RX
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* @tag: RX buffer tag (index of RX buffer queue)
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* @addr: Address of buffer
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*/
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struct frbd {
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u32 tag:16,
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reserved:16;
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u32 reserved2;
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u64 addr;
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} __packed;
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/* URB Descriptor for RX
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* @frbd_tag: Tag from FRBD
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* @status: Status
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*/
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struct urbd1 {
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u32 frbd_tag:16,
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status:1,
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reserved:14,
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fixed:1;
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} __packed;
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/* RFH header in RX packet
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* @packet_len: Length of the data in the buffer
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* @rxq: RX Queue number
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* @cmd_id: Command ID. Not in Use
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*/
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struct rfh_hdr {
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u64 packet_len:16,
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rxq:6,
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reserved:10,
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cmd_id:16,
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reserved1:16;
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} __packed;
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/* Internal data buffer
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* @data: pointer to the data buffer
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* @p_addr: physical address of data buffer
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*/
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struct data_buf {
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u8 *data;
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dma_addr_t data_p_addr;
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};
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/* Index Array */
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struct ia {
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dma_addr_t tr_hia_p_addr;
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u16 *tr_hia;
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dma_addr_t tr_tia_p_addr;
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u16 *tr_tia;
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dma_addr_t cr_hia_p_addr;
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u16 *cr_hia;
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dma_addr_t cr_tia_p_addr;
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u16 *cr_tia;
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};
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/* Structure for TX Queue
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* @count: Number of descriptors
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* @tfds: Array of TFD
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* @urbd0s: Array of URBD0
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* @buf: Array of data_buf structure
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*/
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struct txq {
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u16 count;
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dma_addr_t tfds_p_addr;
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struct tfd *tfds;
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dma_addr_t urbd0s_p_addr;
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struct urbd0 *urbd0s;
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dma_addr_t buf_p_addr;
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void *buf_v_addr;
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struct data_buf *bufs;
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};
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/* Structure for RX Queue
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* @count: Number of descriptors
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* @frbds: Array of FRBD
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* @urbd1s: Array of URBD1
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* @buf: Array of data_buf structure
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*/
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struct rxq {
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u16 count;
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dma_addr_t frbds_p_addr;
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struct frbd *frbds;
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dma_addr_t urbd1s_p_addr;
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struct urbd1 *urbd1s;
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dma_addr_t buf_p_addr;
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void *buf_v_addr;
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struct data_buf *bufs;
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};
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/* struct btintel_pcie_data
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* @pdev: pci device
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* @hdev: hdev device
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* @flags: driver state
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* @irq_lock: spinlock for MSI-X
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* @hci_rx_lock: spinlock for HCI RX flow
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* @base_addr: pci base address (from BAR)
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* @msix_entries: array of MSI-X entries
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* @msix_enabled: true if MSI-X is enabled;
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* @alloc_vecs: number of interrupt vectors allocated
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* @def_irq: default irq for all causes
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* @fh_init_mask: initial unmasked rxq causes
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* @hw_init_mask: initial unmaksed hw causes
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* @boot_stage_cache: cached value of boot stage register
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* @img_resp_cache: cached value of image response register
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* @cnvi: CNVi register value
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* @cnvr: CNVr register value
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* @gp0_received: condition for gp0 interrupt
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* @gp0_wait_q: wait_q for gp0 interrupt
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* @tx_wait_done: condition for tx interrupt
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* @tx_wait_q: wait_q for tx interrupt
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* @workqueue: workqueue for RX work
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* @rx_skb_q: SKB queue for RX packet
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* @rx_work: RX work struct to process the RX packet in @rx_skb_q
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* @dma_pool: DMA pool for descriptors, index array and ci
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* @dma_p_addr: DMA address for pool
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* @dma_v_addr: address of pool
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* @ci_p_addr: DMA address for CI struct
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* @ci: CI struct
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* @ia: Index Array struct
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* @txq: TX Queue struct
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* @rxq: RX Queue struct
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*/
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struct btintel_pcie_data {
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struct pci_dev *pdev;
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struct hci_dev *hdev;
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unsigned long flags;
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/* lock used in MSI-X interrupt */
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spinlock_t irq_lock;
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/* lock to serialize rx events */
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spinlock_t hci_rx_lock;
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void __iomem *base_addr;
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struct msix_entry msix_entries[BTINTEL_PCIE_MSIX_VEC_MAX];
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bool msix_enabled;
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u32 alloc_vecs;
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u32 def_irq;
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u32 fh_init_mask;
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u32 hw_init_mask;
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u32 boot_stage_cache;
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u32 img_resp_cache;
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u32 cnvi;
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u32 cnvr;
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bool gp0_received;
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wait_queue_head_t gp0_wait_q;
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bool tx_wait_done;
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wait_queue_head_t tx_wait_q;
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struct workqueue_struct *workqueue;
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struct sk_buff_head rx_skb_q;
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struct work_struct rx_work;
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struct dma_pool *dma_pool;
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dma_addr_t dma_p_addr;
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void *dma_v_addr;
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dma_addr_t ci_p_addr;
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struct ctx_info *ci;
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struct ia ia;
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struct txq txq;
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struct rxq rxq;
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};
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static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data,
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u32 offset)
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{
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return ioread32(data->base_addr + offset);
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}
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static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data,
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u32 offset, u8 val)
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{
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iowrite8(val, data->base_addr + offset);
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}
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static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data,
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u32 offset, u32 val)
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{
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iowrite32(val, data->base_addr + offset);
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}
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static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data,
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u32 offset, u32 bits)
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{
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u32 r;
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r = ioread32(data->base_addr + offset);
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r |= bits;
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iowrite32(r, data->base_addr + offset);
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}
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static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data,
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u32 offset, u32 bits)
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{
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u32 r;
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r = ioread32(data->base_addr + offset);
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r &= ~bits;
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iowrite32(r, data->base_addr + offset);
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}
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