1200 lines
36 KiB
Plaintext
1200 lines
36 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R-Car V4M (R8A779H0) SoC
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/renesas,r8a779h0-sysc.h>
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/ {
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compatible = "renesas,r8a779h0";
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#address-cells = <2>;
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#size-cells = <2>;
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <825000>;
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clock-latency-ns = <500000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <825000>;
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clock-latency-ns = <500000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&a76_0>;
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};
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core1 {
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cpu = <&a76_1>;
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};
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core2 {
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cpu = <&a76_2>;
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};
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core3 {
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cpu = <&a76_3>;
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};
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};
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};
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a76_0: cpu@0 {
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compatible = "arm,cortex-a76";
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reg = <0>;
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device_type = "cpu";
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power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
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next-level-cache = <&L3_CA76>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;
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operating-points-v2 = <&cluster0_opp>;
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};
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a76_1: cpu@100 {
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compatible = "arm,cortex-a76";
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reg = <0x100>;
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device_type = "cpu";
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power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
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next-level-cache = <&L3_CA76>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;
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operating-points-v2 = <&cluster0_opp>;
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};
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a76_2: cpu@200 {
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compatible = "arm,cortex-a76";
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reg = <0x200>;
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device_type = "cpu";
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power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
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next-level-cache = <&L3_CA76>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;
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operating-points-v2 = <&cluster0_opp>;
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};
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a76_3: cpu@300 {
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compatible = "arm,cortex-a76";
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reg = <0x300>;
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device_type = "cpu";
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power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
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next-level-cache = <&L3_CA76>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;
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operating-points-v2 = <&cluster0_opp>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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local-timer-stop;
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entry-latency-us = <400>;
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exit-latency-us = <500>;
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min-residency-us = <4000>;
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};
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};
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L3_CA76: cache-controller {
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compatible = "cache";
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power-domains = <&sysc R8A779H0_PD_A2E0D0>;
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cache-unified;
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cache-level = <3>;
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};
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};
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extal_clk: extal-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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pmu-a76 {
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compatible = "arm,cortex-a76-pmu";
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interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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/* External SCIF clocks - to be overridden by boards that provide them */
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scif_clk: scif-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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scif_clk2: scif-clk2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a779h0-wdt",
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"renesas,rcar-gen4-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 907>;
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status = "disabled";
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};
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pfc: pinctrl@e6050000 {
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compatible = "renesas,pfc-r8a779h0";
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reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
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<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
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<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
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<0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
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};
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gpio0: gpio@e6050180 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6050180 0 0x54>;
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interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 19>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 915>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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};
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gpio1: gpio@e6050980 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6050980 0 0x54>;
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interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 30>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 915>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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};
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gpio2: gpio@e6058180 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6058180 0 0x54>;
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interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 20>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 916>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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};
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gpio3: gpio@e6058980 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6058980 0 0x54>;
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interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 916>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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};
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gpio4: gpio@e6060180 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6060180 0 0x54>;
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interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 25>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 917>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 917>;
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};
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gpio5: gpio@e6060980 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6060980 0 0x54>;
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interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 21>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 917>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 917>;
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};
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gpio6: gpio@e6061180 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6061180 0 0x54>;
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interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 21>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 917>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 917>;
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};
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gpio7: gpio@e6061980 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6061980 0 0x54>;
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interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 224 21>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 917>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 917>;
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};
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cmt0: timer@e60f0000 {
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compatible = "renesas,r8a779h0-cmt0",
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"renesas,rcar-gen4-cmt0";
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reg = <0 0xe60f0000 0 0x1004>;
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interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 910>;
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clock-names = "fck";
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 910>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,r8a779h0-cmt1",
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"renesas,rcar-gen4-cmt1";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 911>;
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clock-names = "fck";
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 911>;
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status = "disabled";
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};
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cmt2: timer@e6140000 {
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compatible = "renesas,r8a779h0-cmt1",
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"renesas,rcar-gen4-cmt1";
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reg = <0 0xe6140000 0 0x1004>;
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interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 912>;
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clock-names = "fck";
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 912>;
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status = "disabled";
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};
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cmt3: timer@e6148000 {
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compatible = "renesas,r8a779h0-cmt1",
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"renesas,rcar-gen4-cmt1";
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reg = <0 0xe6148000 0 0x1004>;
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interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 913>;
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clock-names = "fck";
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 913>;
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status = "disabled";
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a779h0-cpg-mssr";
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reg = <0 0xe6150000 0 0x4000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a779h0-rst";
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reg = <0 0xe6160000 0 0x4000>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a779h0-sysc";
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reg = <0 0xe6180000 0 0x4000>;
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#power-domain-cells = <1>;
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};
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tsc: thermal@e6198000 {
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compatible = "renesas,r8a779h0-thermal";
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reg = <0 0xe6198000 0 0x200>,
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<0 0xe61a0000 0 0x200>;
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clocks = <&cpg CPG_MOD 919>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 919>;
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#thermal-sensor-cells = <1>;
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};
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 611>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 611>;
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};
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tmu0: timer@e61e0000 {
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compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
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reg = <0 0xe61e0000 0 0x30>;
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interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tuni0", "tuni1", "tuni2";
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clocks = <&cpg CPG_MOD 713>;
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clock-names = "fck";
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 713>;
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status = "disabled";
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};
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tmu1: timer@e6fc0000 {
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compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
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reg = <0 0xe6fc0000 0 0x30>;
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interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
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clocks = <&cpg CPG_MOD 714>;
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clock-names = "fck";
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 714>;
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status = "disabled";
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};
|
|
|
|
tmu2: timer@e6fd0000 {
|
|
compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
|
|
reg = <0 0xe6fd0000 0 0x30>;
|
|
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
|
|
clocks = <&cpg CPG_MOD 715>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 715>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu3: timer@e6fe0000 {
|
|
compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
|
|
reg = <0 0xe6fe0000 0 0x30>;
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
|
|
clocks = <&cpg CPG_MOD 716>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 716>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu4: timer@ffc00000 {
|
|
compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
|
|
reg = <0 0xffc00000 0 0x30>;
|
|
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
|
|
clocks = <&cpg CPG_MOD 717>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 717>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@e6500000 {
|
|
compatible = "renesas,i2c-r8a779h0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe6500000 0 0x40>;
|
|
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 518>;
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 518>;
|
|
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
|
|
<&dmac2 0x91>, <&dmac2 0x90>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@e6508000 {
|
|
compatible = "renesas,i2c-r8a779h0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe6508000 0 0x40>;
|
|
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 519>;
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 519>;
|
|
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
|
|
<&dmac2 0x93>, <&dmac2 0x92>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@e6510000 {
|
|
compatible = "renesas,i2c-r8a779h0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe6510000 0 0x40>;
|
|
interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 520>;
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 520>;
|
|
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
|
|
<&dmac2 0x95>, <&dmac2 0x94>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@e66d0000 {
|
|
compatible = "renesas,i2c-r8a779h0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe66d0000 0 0x40>;
|
|
interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 521>;
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 521>;
|
|
dmas = <&dmac1 0x97>, <&dmac1 0x96>,
|
|
<&dmac2 0x97>, <&dmac2 0x96>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e6540000 {
|
|
compatible = "renesas,hscif-r8a779h0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe6540000 0 0x60>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 514>,
|
|
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 514>;
|
|
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
|
|
<&dmac2 0x31>, <&dmac2 0x30>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif1: serial@e6550000 {
|
|
compatible = "renesas,hscif-r8a779h0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe6550000 0 0x60>;
|
|
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 515>,
|
|
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 515>;
|
|
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
|
|
<&dmac2 0x33>, <&dmac2 0x32>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif2: serial@e6560000 {
|
|
compatible = "renesas,hscif-r8a779h0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe6560000 0 0x60>;
|
|
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 516>,
|
|
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
|
<&scif_clk2>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 516>;
|
|
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
|
|
<&dmac2 0x35>, <&dmac2 0x34>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif3: serial@e66a0000 {
|
|
compatible = "renesas,hscif-r8a779h0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe66a0000 0 0x60>;
|
|
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 517>,
|
|
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 517>;
|
|
dmas = <&dmac1 0x37>, <&dmac1 0x36>,
|
|
<&dmac2 0x37>, <&dmac2 0x36>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
avb0: ethernet@e6800000 {
|
|
compatible = "renesas,etheravb-r8a779h0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6800000 0 0x1000>;
|
|
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 211>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
resets = <&cpg 211>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
iommus = <&ipmmu_hc 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb1: ethernet@e6810000 {
|
|
compatible = "renesas,etheravb-r8a779h0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6810000 0 0x1000>;
|
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 212>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
resets = <&cpg 212>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb2: ethernet@e6820000 {
|
|
compatible = "renesas,etheravb-r8a779h0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6820000 0 0x1000>;
|
|
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 213>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
resets = <&cpg 213>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a779h0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 702>,
|
|
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 702>;
|
|
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
|
|
<&dmac2 0x51>, <&dmac2 0x50>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a779h0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>,
|
|
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 703>;
|
|
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
|
|
<&dmac2 0x53>, <&dmac2 0x52>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6c50000 {
|
|
compatible = "renesas,scif-r8a779h0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 704>,
|
|
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 704>;
|
|
dmas = <&dmac1 0x57>, <&dmac1 0x56>,
|
|
<&dmac2 0x57>, <&dmac2 0x56>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6c40000 {
|
|
compatible = "renesas,scif-r8a779h0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 705>,
|
|
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
|
<&scif_clk2>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 705>;
|
|
dmas = <&dmac1 0x59>, <&dmac1 0x58>,
|
|
<&dmac2 0x59>, <&dmac2 0x58>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e90000 {
|
|
compatible = "renesas,msiof-r8a779h0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6e90000 0 0x0064>;
|
|
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 618>;
|
|
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
|
<&dmac2 0x41>, <&dmac2 0x40>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 618>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6ea0000 {
|
|
compatible = "renesas,msiof-r8a779h0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6ea0000 0 0x0064>;
|
|
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 619>;
|
|
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
|
<&dmac2 0x43>, <&dmac2 0x42>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 619>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6c00000 {
|
|
compatible = "renesas,msiof-r8a779h0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c00000 0 0x0064>;
|
|
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 620>;
|
|
dmas = <&dmac1 0x45>, <&dmac1 0x44>,
|
|
<&dmac2 0x45>, <&dmac2 0x44>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 620>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof3: spi@e6c10000 {
|
|
compatible = "renesas,msiof-r8a779h0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c10000 0 0x0064>;
|
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 621>;
|
|
dmas = <&dmac1 0x47>, <&dmac1 0x46>,
|
|
<&dmac2 0x47>, <&dmac2 0x46>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 621>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof4: spi@e6c20000 {
|
|
compatible = "renesas,msiof-r8a779h0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c20000 0 0x0064>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 622>;
|
|
dmas = <&dmac1 0x49>, <&dmac1 0x48>,
|
|
<&dmac2 0x49>, <&dmac2 0x48>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 622>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof5: spi@e6c28000 {
|
|
compatible = "renesas,msiof-r8a779h0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c28000 0 0x0064>;
|
|
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 623>;
|
|
dmas = <&dmac1 0x4b>, <&dmac1 0x4a>,
|
|
<&dmac2 0x4b>, <&dmac2 0x4a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 623>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dmac1: dma-controller@e7350000 {
|
|
compatible = "renesas,dmac-r8a779h0",
|
|
"renesas,rcar-gen4-dmac";
|
|
reg = <0 0xe7350000 0 0x1000>,
|
|
<0 0xe7300000 0 0x10000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3", "ch4",
|
|
"ch5", "ch6", "ch7", "ch8", "ch9",
|
|
"ch10", "ch11", "ch12", "ch13",
|
|
"ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 709>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 709>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
|
|
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
|
|
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
|
|
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
|
|
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
|
|
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
|
|
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
|
|
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
|
|
};
|
|
|
|
dmac2: dma-controller@e7351000 {
|
|
compatible = "renesas,dmac-r8a779h0",
|
|
"renesas,rcar-gen4-dmac";
|
|
reg = <0 0xe7351000 0 0x1000>,
|
|
<0 0xe7310000 0 0x10000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3", "ch4",
|
|
"ch5", "ch6", "ch7";
|
|
clocks = <&cpg CPG_MOD 710>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 710>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <8>;
|
|
iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
|
|
<&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
|
|
<&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
|
|
<&ipmmu_ds0 22>, <&ipmmu_ds0 23>;
|
|
};
|
|
|
|
mmc0: mmc@ee140000 {
|
|
compatible = "renesas,sdhi-r8a779h0",
|
|
"renesas,rcar-gen4-sdhi";
|
|
reg = <0 0xee140000 0 0x2000>;
|
|
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 706>,
|
|
<&cpg CPG_CORE R8A779H0_CLK_SD0H>;
|
|
clock-names = "core", "clkh";
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 706>;
|
|
max-frequency = <200000000>;
|
|
iommus = <&ipmmu_ds0 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rpc: spi@ee200000 {
|
|
compatible = "renesas,r8a779h0-rpc-if",
|
|
"renesas,rcar-gen4-rpc-if";
|
|
reg = <0 0xee200000 0 0x200>,
|
|
<0 0x08000000 0 0x04000000>,
|
|
<0 0xee208000 0 0x100>;
|
|
reg-names = "regs", "dirmap", "wbuf";
|
|
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 629>;
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 629>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_rt0: iommu@ee480000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xee480000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_rt1: iommu@ee4c0000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xee4c0000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_ds0: iommu@eed00000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeed00000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_hc: iommu@eed40000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeed40000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_ir: iommu@eed80000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeed80000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vc: iommu@eedc0000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeedc0000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_3dg: iommu@eee00000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeee00000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vi0: iommu@eee80000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeee80000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vi1: iommu@eeec0000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeeec0000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vip0: iommu@eef00000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeef00000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779H0_PD_C4>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_mm: iommu@eefc0000 {
|
|
compatible = "renesas,ipmmu-r8a779h0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeefc0000 0 0x20000>;
|
|
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
gic: interrupt-controller@f1000000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x0 0xf1000000 0 0x20000>,
|
|
<0x0 0xf1060000 0 0x110000>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
prr: chipid@fff00044 {
|
|
compatible = "renesas,prr";
|
|
reg = <0 0xfff00044 0 4>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
sensor_thermal_cr52: sensor1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 0>;
|
|
|
|
trips {
|
|
sensor1_crit: sensor1-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
sensor_thermal_ca76: sensor2-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 1>;
|
|
|
|
trips {
|
|
sensor2_crit: sensor2-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|