47 lines
1.3 KiB
C
47 lines
1.3 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Author: Yinbo Zhu <zhuyinbo@loongson.cn>
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* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
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*/
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#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H
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#define __DT_BINDINGS_CLOCK_LOONGSON2_H
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#define LOONGSON2_REF_100M 0
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#define LOONGSON2_NODE_PLL 1
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#define LOONGSON2_DDR_PLL 2
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#define LOONGSON2_DC_PLL 3
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#define LOONGSON2_PIX0_PLL 4
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#define LOONGSON2_PIX1_PLL 5
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#define LOONGSON2_NODE_CLK 6
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#define LOONGSON2_HDA_CLK 7
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#define LOONGSON2_GPU_CLK 8
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#define LOONGSON2_DDR_CLK 9
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#define LOONGSON2_GMAC_CLK 10
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#define LOONGSON2_DC_CLK 11
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#define LOONGSON2_APB_CLK 12
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#define LOONGSON2_USB_CLK 13
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#define LOONGSON2_SATA_CLK 14
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#define LOONGSON2_PIX0_CLK 15
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#define LOONGSON2_PIX1_CLK 16
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#define LOONGSON2_BOOT_CLK 17
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#define LOONGSON2_OUT0_GATE 18
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#define LOONGSON2_GMAC_GATE 19
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#define LOONGSON2_RIO_GATE 20
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#define LOONGSON2_DC_GATE 21
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#define LOONGSON2_GPU_GATE 22
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#define LOONGSON2_DDR_GATE 23
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#define LOONGSON2_HDA_GATE 24
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#define LOONGSON2_NODE_GATE 25
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#define LOONGSON2_EMMC_GATE 26
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#define LOONGSON2_PIX0_GATE 27
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#define LOONGSON2_PIX1_GATE 28
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#define LOONGSON2_OUT0_CLK 29
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#define LOONGSON2_RIO_CLK 30
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#define LOONGSON2_EMMC_CLK 31
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#define LOONGSON2_DES_CLK 32
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#define LOONGSON2_I2S_CLK 33
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#define LOONGSON2_MISC_CLK 34
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#endif
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